;---------------------------------------------------------------------------
;
; FILE NAME: Si8250.INC
; TARGET MCUs: Si8250, Si8251, Si8252
; DESCRIPTION: Register/bit definitions for the Si825x product family.
;
; REVISION 1.0
;
;---------------------------------------------------------------------------

;REGISTER DEFINITIONS
;
P0		    DATA 080H    ; PORT0 
SP		    DATA 081H    ; STACK POINTER
DPL		    DATA 082H    ; DATA POINTER- LOW BYTE
DPH		    DATA 083H    ; DATA POINTER- HIGH BYTE
CRC0CN	  DATA 084H    ; CRC CONTROL
CRC0IN	  DATA 085H    ; CRC DATA INPUT
CRC0DAT	  DATA 086H    ; CRC RESULTS REGISTER
PCON	    DATA 087H    ; POWER CONTROL
TCON	    DATA 088H    ; TIMER CONTROL
TMOD	    DATA 089H    ; TIMER MODE
TL0		    DATA 08AH    ; TIMER 0 - LOW BYTE
TL1		    DATA 08BH    ; TIMER 1 - LOW BYTE
TH0		    DATA 08CH    ; TIMER 0 - HIGH BYTE
TH1		    DATA 08DH    ; TIMER 1 - HIGH BYTE
CKCON	    DATA 08EH    ; CLOCK CONTROL
PSCTL	    DATA 08FH    ; PROGRAM STORE READ/WRITE CONTROL

P1		    DATA 090H    ; PORT 1
TMR3CN	  DATA 091H    ; TIMER 3 CONTROL
TMR3RLL	  DATA 092H    ; TIMER3 LOW RELOAD
TMR3RLH	  DATA 093H    ; TIMER3 HIGH RELOAD
TMR3L	    DATA 094H    ; TIMER3 LOW BYTE
TMR3H	    DATA 095H    ; TIMER 3 HIGH BYTE
REFDAC0L	DATA 096H    ; RDAC 0 DATA WORD LSB REGISTER
REFDAC0H	DATA 097H    ; RDAC 0 CONTROL REGISTER

SCON0	    DATA 098H    ; SERIAL PORT CONTROL
SBUF0	    DATA 099H    ; SERIAL PORT BUFFER
CPT1CN	  DATA 09AH    ; COMPARATOR 1 CONTROL
CPT0CN	  DATA 09BH    ; COMPARATOR 0 CONTROL
OSCLCN	  DATA 09CH    ; LOW FREQUENCY OSCILLATOR CONTROL
CPT0MD	  DATA 09DH    ; COMPARATOR 0 MODE
CPT1MX	  DATA 09EH    ; COMPARATOR 1 MUX SELECT
CPT0MX	  DATA 09FH    ; COMPARATOR 0 MUX SELECT

IPKCN		  DATA 0A0H    ; DSR FLAG REGISTER (DBI ONLY)
P2			  DATA 0A0H    ; PORT 2 (non-DBI only)
DPWMLCD0	DATA 0A1H    ; DPWM LCD0 REGISTER
DPWMLCD1	DATA 0A2H    ; DPWM LCD1 REGISTER
DPWMLCD2	DATA 0A3H    ; DPWM LCD2 REGISTER
P0MDOUT		DATA 0A4H    ; PORT 0 MODE OUT
P1MDOUT		DATA 0A5H    ; PORT 1 MODE OUT
DPWMOUT		DATA 0A6H    ; DPWM CONTROL REGISTER
SFRPAGE		DATA 0A7H    ; SFR PAGE REGISTER

IE		    DATA 0A8H    ; INTERRUPT ENABLE
CLKSEL	  DATA 0A9H    ; CLOCK SELECT REGISTER
EMI0CN	  DATA 0AAH    ; EMIF CONTROL
ADC0ADDR	DATA 0ABH    ; ADC0 ADDRESS REGISTER
BP1L	    DATA 0ABH    ; BREAKPOINT 1 - LOW BYTE
ADC0DATA	DATA 0ACH    ; ADC0 DATA REGISTER
BP1H	    DATA 0ACH    ; BREAKPOINT 1 - HIGH BYTE
DPWMADDR	DATA 0ADH    ; DPWM INDIRECT ADDRESS REGISTER
XADRL	    DATA 0ADH    ; XRAM SFR PORT LOW ADDRESS
ADDRL	    DATA 0AEH    ; FLASH ADDRESS LOW
DPWMDATA	DATA 0AEH    ; DPWM INDIRECT DATA REGISTER
ONESHOT	  DATA 0AFH    ; ONESHOT CONTROL REGISTER
ADDRH	    DATA 0AFH    ; FLASH ADDRESS HIGH


P0ODEN	  DATA 0B0H    ; P0 OVERDRIVE ENABLE
OSCXCN	  DATA 0B1H    ; EXTERNAL OSCILLATOR CONTROL
OSCICN	  DATA 0B2H    ; INTERNAL OSCILLATOR CONTROL
OSCICL	  DATA 0B3H    ; INTERNAL OSCILLATOR CALIBRATION
DSRCMD	  DATA 0B4H    ; DSR COMMAND REGISTER
ADC0STA0  DATA 0B5H    ; ADC0 Interrupt Status
FLSCL	    DATA 0B6H    ; FLASH MEMORY TIMING PRESCALER
FLKEY	    DATA 0B7H    ; FLASH LOCK REGISTER

IP		    DATA 0B8H    ; INTERRUPT PRIORITY
PLLCN	    DATA 0B9H    ; PLL200 CONTROL REGISTER
ADC0TK	  DATA 0BAH    ; IDAC 0 CONTROL REGISTER
ADC0MX	  DATA 0BBH    ; ADC 0 MUX CONTROL
ADC0CF	  DATA 0BCH    ; ADC 0 CONFIG REGISTER
ADC0L	    DATA 0BDH    ; ADC 0 LSB RESULT
ADC0H	    DATA 0BEH    ; ADC 0 MSB RESULT
ADC0STA1  DATA 0BFH    ; FLASH DATA REGISTER


SMB0CN	  DATA 0C0H    ; SM BUS CONTROL
SMB0CF	  DATA 0C1H    ; SM BUS CONFIG
SMB0DAT	  DATA 0C2H    ; SM BUS DATA
ADC0GTL	  DATA 0C3H    ; ADC 0 GREATER THAN LSB
ADC0GTH	  DATA 0C4H    ; ADC 0 GREATER THAN MSB
ADC0LTL	  DATA 0C5H    ; ADC 0 LESS THAN LSB
ADC0LTH	  DATA 0C6H    ; ADC 0 LESS THAN MSB
ADC0LM0	  DATA 0C7H    ; PORT 1 MASK REGISTER
XADRH	    DATA 0C7H    ; XRAM SFR PORT HIGH ADDRESS


TMR2CN	  DATA 0C8H    ; TIMER 2 LOW BYTE
ADC0LM1	  DATA 0C9H    ; REGULATOR CONTROL
TMR2RLL	  DATA 0CAH    ; TIMER 2 - LOW BYTE
TMR2RLH	  DATA 0CBH    ; TIMER 2 - HIGH BYTE
TMR2L	    DATA 0CCH    ; TIMER 2 - LOW BYTE
TMR2H	    DATA 0CDH    ; TIMER 2 - HIGH BYTE
PIDCN	    DATA 0CEH    ; BREAKPOINT 2 - LOW BYTE
PIDUN	    DATA 0CFH    ; PID OUTPUT REGISTER
BP2H	    DATA 0CFH    ; BREAKPOINT 2 - HIGH BYTE

PSW		    DATA 0D0H    ; PROGRAM STATUS WORD
REF0CN	  DATA 0D1H    ; VOLTAGE REFERENCE 0 CONTROL
ICYCST	  DATA 0D2H    ; PEAK CURRENT DETECTOR CONTROL REGISTER
BP3L	    DATA 0D2H    ; BREAKPOINT 3 LOW BYTE
TRDETCN	  DATA 0D3H    ; ADC TRANSIENT DETECT CONTROL REGISTER
BP3H	    DATA 0D3H    ; BREAKPOINT 3 HIGH BYTE
P0SKIP	  DATA 0D4H    ; PORT 0 SKIP
P1SKIP	  DATA 0D5H    ; PORT 1 SKIP
LEBCN	    DATA 0D6H    ; Leading edge blanking control register
OCPCN	    DATA 0D7H    ; OVERCURRENT PROTECTION CONTROL REGISTER


PCA0CN		DATA 0D8H    ; PCA 0 COUNTER CONTROL
PCA0MD		DATA 0D9H    ; PCA 0 COUNTER MODE
PCA0CPM0	DATA 0DAH    ; CONTROL REGISTER FOR PCA 0 MODULE 0
PCA0CPM1	DATA 0DBH    ; CONTROL REGISTER FOR PCA 0 MODULE 1
PCA0CPM2	DATA 0DCH    ; CONTROL REGISTER FOR PCA 0 MODULE 2
PIDA0CN		DATA 0DDH    ; PID A0 COEFFICIENT
PIDDECCN  DATA 0DEH    ; PID DECIMATION COEFFICIENT
CRC0FLIP	DATA 0DFH    ; PID CONTROL REGISTER
ERASE		  DATA 0DFH    ; FLASH ERASE REGISTER


P2_C2	    DATA 0E0H    ; P2 (C2 XFMR ONLY)
ACC		    DATA 0E0H    ; ACCUMULATOR
XBR0	    DATA 0E1H    ; CROSSBAR CONFIGURATION REGISTER 0
XBR1	    DATA 0E2H    ; CROSSBAR CONFIGURATION REGISTER 1
CCH0CN	  DATA 0E3H    ; CACHE CONTROL REGISTER
CCHADDR	  DATA 0E3H    ; CACHE ADDRESS REGISTER
IT01CF	  DATA 0E4H    ; INT0/1 MUX CONTROL REGISTER
DSRROP	  DATA 0E5H    ; DSR OPERAND REGISTER
PIDA3CN	  DATA 0E5H    ; PID A3 COEFFICIENT
EIE1	    DATA 0E6H    ; EXTERNAL INTERRUPT ENABLE 1
EIE2	    DATA 0E7H    ; EXTERNAL INTERRUPT ENABLE 2
CCHDATA	  DATA 0E7H    ; CACHE DATA REGIATER


ADC0CN	  DATA 0E8H    ; ADC 0 CONTROL
PCA0CPL1	DATA 0E9H    ; PCA 0 COMPARE/CAPTURE 0 - LOW BYTE
PCA0CPH1	DATA 0EAH    ; PCA 0 COMPARE/CAPTURE 0 - HIGH BYTE
PCA0CPL2	DATA 0EBH    ; PCA 0 COMPARE/CAPTURE 1 - LOW BYTE
PCA0CPH2	DATA 0ECH    ; PCA 0 COMPARE/CAPTURE 1 - HIGH BYTE
PIDA1CN	  DATA 0EDH    ; PID A1 COEFFICIENT
PIDA2CN	  DATA 0EEH    ; PID A2 COEFFICIENT
RSTSRC	  DATA 0EFH    ; RESET SOURCE


B		      DATA 0F0H    ; B REGISTER
REFDACMD	DATA 0F1H    ; REFDAC MODE REGISTER
P1MDIN	  DATA 0F2H    ; P1 INPUT MODE REGISTER
PIDKPCN	  DATA 0F3H    ; PID KP COEFFICIENT
PIDKICN	  DATA 0F4H    ; PID KI COEFFICIENT
PIDKDCN	  DATA 0F5H    ; PID KD COEFFICIENT
EIP1	    DATA 0F6H    ; EXTERNAL INTERRUPT PRIORITY REGISTER 1
EIP2	    DATA 0F7H    ; EXTERNAL INTERRUPT PRIORITY REGISTER 2


DPWMCNTL	DATA 0F8H    ; DPWM CONTROL
PCA0L		  DATA 0F9H    ; PCA 0 TIMER - LOW BYTE
PCA0H		  DATA 0FAH    ; PCA 0 TIMER - HIGH BYTE
PCA0CPL0	DATA 0FBH    ; PCA 0 COMPARE/CAPTURE 0 - LOW BYTE
PCA0CPH0	DATA 0FCH    ; PCA 0 COMPARE/CAPTURE 0 - HIGH BYTE
ADC1DAT		DATA 0FDH    ; ADC1 DATA REGISTER
ADC1CN		DATA 0FEH    ; ADC1 CONTROL REGISTER
VDM0CN    DATA 0FFH    ; VDD MONITOR CONTROL     

;
;------------------------------------------------------------------------------
;BIT DEFINITIONS
;

;TCON 0X88

IT0	      BIT TCON.0    ;EXTERNAL INTERRUPT 0 TYPE
IE0	      BIT TCON.1    ;EXTERNAL INTERRUPT 0 EDGE FLAG
IT1	      BIT TCON.2    ;EXTERNAL INTERRUPT 1 TYPE
IE1	      BIT TCON.3    ;EXTERNAL INTERRUPT 1 EDGE FLAG
TR0	      BIT TCON.4    ;TIMER 0 ON/OFF CONTROL
TF0	      BIT TCON.5    ;TIMER 0 OVERFLOW FLAG
TR1	      BIT TCON.6    ;TIMER 1 ON/OFF CONTROL
TF1	      BIT TCON.7    ;TIMER 1 OVERFLOW FLAG

;TMR2CN  0XC8

TF2H	    BIT TMR2CN.7    ;T2 HIGH BYTE OVERFLOW FLAG
TF2L	    BIT TMR2CN.6    ;T2 LOW BYTE OVERFLOW FLAG
IE2L	    BIT TMR2CN.5    ;T2 LOW BYTE FLAG ENABLE
T2CAP	    BIT TMR2CN.4    ;T2 CAPTURE ENABLE
TS2	      BIT TMR2CN.3    ;T2 SPLIT-MODE ENABLE
TR2	      BIT TMR2CN.2    ;T2 ON/OFF CONTROL
TRS2	    BIT TMR2CN.1    ;XCLK/RCLK SELECT
TX2	      BIT TMR2CN.0    ;T2 CLK/8 CLOCK SOURCE

;SCON0  0X98

RI0	      BIT SCON0.0    ;RECEIVE INTERRUPT FLAG
TI0	      BIT SCON0.1    ;TRANSMIT INTERRUPT FLAG
RB80	    BIT SCON0.2    ;RECEIVE BIT 8
TB80	    BIT SCON0.3    ;TRANSMIT BIT 8
REN0	    BIT SCON0.4    ;RECEIVE ENABLE
MCE0	    BIT SCON0.5    ;MULTIPROCESSOR COMMUNICATION ENABLE
SM1	      BIT SCON0.6    ;SERIAL MODE CONTROL BIT 1
S0MODE	  BIT SCON0.7    ;SERIAL MODE CONTROL BIT 0

;IE 0XA8

EX0ENABX  BIT IE.0    ;EXTERNAL INTERRUPT 0 ENABLE
EOCP      BIT IE.1    ;OVERCURRENT PROTECTION INTERRUPT ENABLE
EAIN0     BIT IE.2    ;ADC0 VIN WINDOW INTERRUPT ENABLE
ES0	      BIT IE.3    ;UART INTERRUPT ENABLE
ETRDET    BIT IE.4    ;TRANSIENT DETECTOR INTERRUPT ENABLE
ECP0      BIT IE.5    ;COMPARATOR INTERRUPT ENABLE
EEN       BIT IE.6    ;GENERAL PURPOSE FLAG BIT
EA	      BIT IE.7    ;GLOBAL INTERRUPT ENABLE

;IP 0XB8

PX0	      BIT IP.0    ;EXTERNAL INTERRUPT 0 PRIORITY
POCP      BIT IP.1    ;OVERCURRENT PROTECTION PRIORITY
PAIN0	    BIT IP.2    ;EXTERNAL INTERRUPT 1 PRIORITY
PT1	      BIT IP.3    ;TIMER 1 PRIORITY
PTRDET    BIT IP.4    ;SERIAL PORT PRIORITY
PT2       BIT IP.5    ;TIMER 2 PRIORITY
PEN       BIT IP.6    ;INT1 PRIORITY

;SMB0CN  0XC0

SI 	      BIT SMB0CN.0    ;SMBUS 0 INTERRUPT FLAG
ACK	      BIT SMB0CN.1    ;SMBUS 0 ACK BIT
ARBLOST   BIT SMB0CN.2    ;SMBUS 0 ARBITRATION FLAG
ACKRQ	    BIT SMB0CN.3    ;SMBUS 0 ACK REQUEST FLAG
STO	      BIT SMB0CN.4    ;SMBUS 0 STOP FLAG
STA	      BIT SMB0CN.5    ;SMBUS 0 START FLAG
TXMODE	  BIT SMB0CN.6    ;SMBUS 0 TRANSMIT MODE FLAG
MASTER	  BIT SMB0CN.7    ;SMBUS 0 MASTER MODE FLAG

;PSW 0XD0

P		      BIT PSW.0    ;ACCUMULATOR PARITY FLAG
F1		    BIT PSW.1    ;USER FLAG 1
OV		    BIT PSW.2    ;OVERFLOW FLAG
RS0	      BIT PSW.3    ;REGISTER BANK SELECT 0
RS1	      BIT PSW.4    ;REGISTER BANK SELECT 1
F0 	      BIT PSW.5    ;USER FLAG 0
AC		    BIT PSW.6    ;AUXILIARY CARRY FLAG
CY 	      BIT PSW.7    ;CARRY FLAG

;PCA0CN  0XD8

CCF0	    BIT PCA0CN.0    ;PCA 0 MODULE 0 INTERRUPT FLAG
CCF1	    BIT PCA0CN.1    ;PCA 0 MODULE 1 INTERRUPT FLAG
CCF2	    BIT PCA0CN.2    ;PCA 0 MODULE 2 INTERRUPT FLAG
CCF3 	    BIT PCA0CN.3    ;PCA 0 MODULE 3 INTERRUPT FLAG
CCF4	    BIT PCA0CN.4    ;PCA 0 MODULE 4 INTERRUPT FLAG
CCF5	    BIT PCA0CN.5; 	;PCA 0 MODULE 5 INTERRUPT FLAG
CR		    BIT PCA0CN.6    ;PCA 0 COUNTER RUN CONTROL BIT
CF		    BIT PCA0CN.7    ;PCA 0 COUNTER OVERFLOW FLAG

;ADC0CN 0XE8

ADC0CM0	  BIT ADC0CN.0    ;ADC 0 START OF CONVERSION MODE BIT 0
ADC0CM1	  BIT ADC0CN.1    ;ADC 0 START OF CONVERSION MODE BIT 1
ADC0ADJL	BIT ADC0CN.2    ;ADC 0 ADJUST DATA LEFT
ADC0WINT	BIT ADC0CN.3    ;ADC 0 WINDOW COMPARE INTERRUPT FLAG
ADC0BUSY	BIT ADC0CN.4    ;ADC 0 BUSY FLAG
ADC0INT	  BIT ADC0CN.5    ;ADC 0 CONVERSION COMPLETE INTERRUPT FLAG
ADC0BE		BIT ADC0CN.6; 	;ADC 0 BURST ENABLE
ADC0EN		BIT ADC0CN.7    ;ADC 0 ENABLE

;DPWMCNTL 0XF8

EOFINT		BIT DPWMCNTL.0    ;END OF FRAME INTERRUPT
DPWMINPUT BIT DPWMCNTL.1    ;DPWM INPUT MUX CONTROL BIT
ENABXPOL	BIT DPWMCNTL.2    ;HARDWARE ENABLE POLARITY
SWBP		  BIT DPWMCNTL.3    ;SOFTWARE BYPASS CONTROL
EMGY_EN	  BIT DPWMCNTL.4    ;EMERGENCY ENABLE/ DISABLE
HWBP_EN	  BIT DPWMCNTL.5    ;HARDWARE BYPASS ENABLE
SYNC_EN	  BIT DPWMCNTL.6    ;SYNC INPUT FUNCTION ENABLE
DPWM_EN	  BIT DPWMCNTL.7    ;DPWM ENABLE/ DISABLE BIT 
